Stacks of integrated circuit structures with memory and back-side power delivery

Abstract

IC devices with stacks of IC structures with memory and back-end power delivery are disclosed, where different IC structures of a stack are bonded together. An example IC device includes a first and a second IC structures. The first IC structure includes a layer of memory cells, a power delivery structure at the back side of the layer of memory cells, and a layer of signal interconnects at a front side of the layer of memory cells. The second IC structure is attached to the layer of signal interconnects of the first IC structure and includes a layer of memory cells and a power delivery structure at a back side of the layer of memory cells of the second IC structure. The layer of signal interconnects of the first IC structure may be configured to provide signals to memory cells of, both, the first and the second IC structures.

Dependencies are inferred from the claim text.