US 2023/0053461 A1 · SEMICONDUCTOR STRUCTURE AND MASK PLATE STRUCTURE

Abstract

Embodiments of the present application relate to the field of semiconductor manufacturing technologies, in particular to a semiconductor structure and a mask plate structure. The semiconductor structure includes a substrate, where the substrate is provided therein with active areas and a plurality of bit line structures arranged at intervals in parallel in the substrate. A plurality of word line structures are arranged at intervals in parallel in the substrate. The word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate. Capacitor plugs are located in the grids. Projection of each of the capacitor plugs on the substrate covers a part of one of the active areas. Cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

Claims15

Dependent claims

A semiconductor structure, comprising:

a substrate, wherein the substrate is provided therein with active areas and word line structures, and the word line structures are arranged at intervals in parallel in the substrate;
bit line structures, wherein the bit line structures are arranged at intervals in parallel on the substrate, and the word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate;
and
capacitor plugs, located in the grids, wherein projection of each of the capacitor plugs on the substrate covers a part of one of the active areas, and cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

1 more element

A mask plate structure, comprising a mask component, wherein a mask pattern is provided on the mask component, and the mask component is used to cover a semiconductor structure, such that capacitor plugs are formed on the semiconductor structure by using the mask component;

the semiconductor structure comprises a substrate and a plurality of word line structures arranged at intervals in parallel on the substrate, the substrate is provided therein with active areas and bit line structures, the bit line structures are arranged at intervals in parallel on the substrate, the word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate;
and
the capacitor plugs are located in the grids, projection of each of the capacitor plugs on the substrate covers a part of one of the active areas, and cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

Dependencies are inferred from the claim text.

Semiconductor structure and mask plate structure

Life of this patent

Semiconductor structure and mask plate structure

Life of this patent

Abstract

Claims15