Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts

A semiconductor memory device, comprising:

• a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
• a plurality of vertical pillars that extend above the substrate in a third direction that is perpendicular to the first and second directions;
• a plurality of contacts that vertically overlap and electrically connect to respective ones of the vertical pillars;
• and
• a first bit line and a second bit line, the first and second bit lines each extending in the second direction and spaced apart from each other in the first direction;
• wherein at least one of the plurality of contacts is shifted with respect to the respective ones of the vertical pillars thereunder in a direction not parallel to the second direction,
• wherein a first subset of the contacts that are electrically connected to the first bit line are aligned in a first row that extends in the second direction and a second subset of the contacts that are electrically connected to the second bit line are aligned in a second row that extends in the second direction.