Method of manufacturing high resistivity soi substrate with reduced interface conducitivity

A method of preparing a silicon-on-insulator structure, the method comprising:

• bonding a front surface of a single crystal silicon handle substrate and a front surface of a single crystal silicon donor substrate;
• wherein the single crystal silicon handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon handle substrate and the other of which is a back surface of the single crystal silicon handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon handle substrate, and a central plane of the single crystal silicon handle substrate between the front and back surfaces of the single crystal silicon handle substrate, wherein the single crystal silicon handle substrate has a minimum bulk resistivity of 100 ohm-cm, the front surface of the single crystal silicon handle substrate comprises an oxidized front surface layer, and the single crystal silicon handle substrate comprises a nanocavity layer having an average depth, D3, as measured from a point on the oxidized front surface of the single crystal silicon handle substrate and toward the central plane of the single crystal silicon handle substrate;
• and
• wherein the single crystal silicon donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon donor substrate and the other of which is a back surface of the single crystal silicon donor substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon donor substrate, and a central plane of the single crystal silicon donor substrate between the front and back surfaces of the single crystal silicon donor substrate, wherein the single crystal silicon donor substrate comprises a cleave plane.

A method of preparing a silicon-on-insulator structure, the method comprising:

• implanting He ions through a front surface of a single crystal semiconductor handle wafer to thereby form an implant plane having a peak depth, D1, as measured from the front surface of the single crystal semiconductor handle wafer and toward a central plane of the single crystal semiconductor handle wafer, the single crystal semiconductor handle wafer comprising two major, generally parallel surfaces, one of which is the front surface of the handle wafer and the other of which is a back surface of the handle wafer, a circumferential edge joining the front and back surfaces of the handle wafer, a bulk single crystal semiconductor region, and the central plane of the single crystal semiconductor handle wafer between the front and back surfaces of the single crystal semiconductor handle wafer, wherein the single crystal semiconductor handle wafer has a minimum bulk resistivity of at least 100 ohm-cm, the peak depth D1 comprises the depth of the highest concentration of He ions in the single crystal semiconductor handle wafer, and the peak depth D1 is no greater than about 5 micrometers from the front surface of the single crystal semiconductor handle wafer;
• thermal annealing the He ion implanted single crystal semiconductor handle wafer to form a nanocavity layer in the single crystal semiconductor handle wafer;
• and
• bonding the front surface of the single crystal semiconductor handle wafer and a front surface of a single crystal silicon donor substrate, wherein the single crystal silicon donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal silicon donor substrate and the other of which is a back surface of the single crystal silicon donor substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon donor substrate, a central plane of the single crystal silicon donor substrate between the front and back surfaces of the single crystal silicon donor substrate, and a cleave plane.