Method of protecting an interlayer dielectric layer and structure formed thereby

A semiconductor device comprising:

• a substrate;
• a first gate structure on the substrate;
• a second gate structure on the substrate;
• an interlayer dielectric (ILD) layer for electrically insulating the first gate structure from the second gate structure on the substrate, wherein a top surface of the ILD layer is lower than top surfaces of the first and second gate structures;
• a contact etch stop layer (CESL) surrounding the ILD layer;
• and
• a protective layer on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, wherein a top surface of the protective layer is level with the top surfaces of the first and second gate structures, and a width of the protective layer is equal to a width of the ILD layer.

A method of protecting an interlayer dielectric (ILD) layer, the method comprising:

• forming a gate structure over a substrate;
• forming a silicide region adjacent to the gate structure;
• forming the ILD layer over the substrate;
• forming a cavity in a top portion of the ILD layer, wherein the ILD layer is between a bottom of the cavity and the silicide region;
• filling the cavity with a protective layer formed over the ILD layer and the gate structure;
• and
• planarizing the protective layer, wherein a top surface of the planarized protective layer is level with a top surface of the gate structure.