Monitoring test element groups (tegs) for etching process and methods of manufacturing a semiconductor device using the same

A method of manufacturing a semiconductor device comprising:

• fanning a first insulating interlayer on a substrate including a chip region and a scribe lane;
• forming a first etch stopping layer on the first insulating interlayer;
• forming a second insulating interlayer on the first etch stopping layer;
• forming a first opening portion in the second insulating interlayer in the scribe region by performing a first etching process which partially etches the second insulating interlayer to form a partial contact hole in the scribe region which does not expose the first etch stopping layer in the scribe region, a second etching process which etches the second insulating interlayer until the etch stopping layer is exposed in the scribe region and a third etching process which etches the first etch stopping layer exposed in the scribe region;
• forming a second opening portion in the second insulating layer near the first opening portion in the scribe region by performing only the second and third etching processes and wherein the first etch stopping layer is not exposed by the second opening portion;
• and
• measuring a depth of the partial contact hole formed by the first etching process using a depth of the first opening portion and a depth of the second opening portion.

A method of manufacturing a semiconductor device comprising:

• forming a first insulating interlayer on a substrate including a chip region and a scribe lane;
• forming a first metal pattern in the first insulating interlayer in the chip region and a second metal pattern in the first insulating interlayer in the scribe lane;
• forming a second insulating interlayer on the first insulating interlayer;
• forming a third insulating interlayer on the second insulating interlayer;
• forming a third metal pattern in the third insulating interlayer in the chip region and a fourth metal pattern in the third insulating interlayer in the scribe lane;
• forming a first etch stopping layer on the third insulating interlayer and a fourth insulating interlayer on the first etch stopping layer;
• forming a first hard mask pattern on the fourth insulating interlayer and a second mask pattern on the first hard mask pattern;
• performing a first etching process which includes etching the fourth insulating interlayer to form a partial contact hole in the chip region and in the scribe lane facing the second metal pattern formed in the scribe region using the second hard mask pattern, wherein the first etch stopping layer is not exposed by the partial contact holes in the chip region and the scribe lane;
• performing a second etching process using the first hard mask pattern which includes etching the fourth insulating interlayer including a bottom portion of the partial contact hole in the chip region to form a preliminary first contact hole exposing the first etch stopping layer in the chip region and a preliminary first trench connected to the preliminary first contact hole in the chip region, and etching the fourth insulating interlayer including a bottom portion of the partial contact hole in the scribe region and another portion of the fourth insulating interlayer near the partial contact hole in the scribe region to respectively form a preliminary first opening portion in the scribe region exposing the first etch stopping layer and a preliminary second opening portion in the scribe lane which does not expose the first etch stopping layer and which faces the fourth metal pattern formed in the scribe region;
• performing a third etching process using the first hard mask pattern which includes etching the fourth insulating interlayer and the first etch stopping layer exposed by the preliminary first contact hole to form a first contact hole in the chip region exposing the third metal pattern and a first trench connected with the first contact hole, etching a portion of the first etch stopping layer exposed by the preliminary first opening portion in the scribe lane to form a first opening portion in the scribe lane and etching the fourth insulating interlayer at a bottom of the preliminary second opening portion in the scribe lane to form a second opening portion in the scribe lane having a depth less a depth of the fourth insulating interlayer and less than a depth of the first opening portion;
• and
• measuring a depth of the partial contact hole formed in the scribe lane by the first etching process using a difference between the depth of the first opening portion and the depth of the second opening portion formed in the scribe region.