US 2012/0074539 A1Published application

Device and methods for electrostatic discharge protection

AssigneeSemiconductor Manufacturing International (Shanghai) Corporation

InventorsTa Lee Yu, Chi Kang Liu, Jing Liu

Life of this patent

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Abstract

An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Claims20

Dependent claims

An electrostatic discharge protective device, the device comprising:

a semiconductor substrate;
a first N well region provided in the semiconductor substrate, the first N well region comprising:
a first heavily doped P+ region and a first heavily doped N+ region, the first heavily doped N+ region being coupled to a Vdd potential;
a first spacing between the first heavily doped P+ region and the first heavily doped N+ region, the spacing being a portion of the first N well region;
a second N well region provided in the semiconductor substrate, the second N well region comprising:
a second heavily doped P+ region and a second heavily doped N+ region;
a second spacing between the second heavily doped P+ region and the second heavily doped N+ region, the second spacing being a portion of the second N well region;
a plurality of third N well regions, one of the plurality of third N well regions being disposed between the first and second N well regions at a spacing and comprising:
a third heavily doped P+ region and a third heavily doped N+ region, the third heavily doped N+ region being electrically coupled to the first heavily coped P+ region, and the third heavily doped P+ region being electrically coupled to the second heavily doped N+ region;
a third spacing between the third heavily doped P+ region and the third heavily doped N+ region, the third spacing being a portion of the third N well region;
and
a P well region provided in the semiconductor substrate abutting the second N well region;
the P well region comprises:
a fourth heavily doped P+ region and a fourth heavily doped N+ region, the fourth heavily doped P+ region being coupled to a Vss potential, the fourth heavily doped N+ region being coupled to the second heavily doped P+ region in common with an input/output pad of an integrated circuit;
a fourth spacing between the fourth heavily doped P+ region and the fourth heavily doped N+ region, the fourth spacing being a portion of the P well region;
wherein a capacitance between the input/output pad and the first heavily doped N+ region or between the input/output pad and the fourth heavily doped P+ region is less than 0.1 pF.

13 more elements

An electrostatic discharge protective device, the device comprising:

a semiconductor substrate;
a first region and a second region in the semiconductor substrate;
a spacing between the first region and the second region, the spacing being a portion of the semiconductor substrate;
a first N well region provided in the first region, the first N well region comprising:
a first heavily doped P+ region and a first heavily doped N+ region, the first heavily doped N+ region being coupled to a Vdd potential;
a first spacing between the first heavily doped P+ region and the first heavily doped N+ region, the first spacing being a portion of the first N well region;
a second N well region provided in the first region, the second N well region comprising:
a second heavily doped P+ region and a second heavily doped N+ region, the second heavily doped N+ region being electrically couple to the first P+ region;
a second spacing between the second heavily doped P+ region and the second heavily doped N+ region, the second spacing being a portion of the second N well region;
a plurality of third N well regions in the first region, one of the plurality of third N well regions being disposed between the first and second N well regions and comprising:
a third heavily doped P+ region and a third heavily doped N+ region, the third heavily doped N+ region being electrically coupled to the first heavily doped P+ region, and the third heavily doped P+ region being electrically coupled to the second heavily doped N+ region;
a third spacing between the third heavily doped P+ region and the third heavily doped N+ region, the third spacing being a portion of the third N well region;
a fourth N well region provided in the second region, the fourth N well region comprising:
a fourth heavily doped N+ region, the fourth heavily doped N+ region being electrically coupled to the second heavily doped P+ region in common with an input/output pad of an internal circuit;
and
a P well region provided in the second region abutting the fourth N well region, the P well region comprising:
a fourth heavily doped P+ region, the fourth heavily doped P+ region being coupled to a Vss potential;
wherein:
each of the plurality of third N well regions is spaced apart from an adjacent third N well region including the first and second N well regions at a spacing length, the spacing length being a portion of the first region, and
a capacitance between the input/output pad and the first heavily doped N+ region or between the input/output pad and the fourth heavily doped P+ region is less than 0.1 pF.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/076,269Filed 30 Mar 2011
Priority: CN 201010144264.62 Apr 2010
Published: 29 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
H10W 72/90
Interconnections or connectors in packages: bond pads, in general
H10D
Inorganic electric semiconductor devices
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by

Family

US 8,368,186 B2Related patent
US 2012/0074539 A1This patent

From the US filing history. Foreign family members aren’t listed.

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