Gate line edge roughness reduction by using 2P/2E process together with high temperature bake
AssigneeTexas Instruments Incorporated
InventorsYiming Gu, James Walter Blatchford
Life of this patent
Estimating the term…
Abstract
A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
Claims21
A method of patterning a plurality of polysilicon structures, comprising:
- forming a polysilicon layer over a semiconductor body;
- performing a first patterning of the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER);
- and
- performing a second patterning of the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
A method of patterning a single polysilicon layer with two distinct, separate patterning processes, comprising:
- forming a first photoresist layer over the single polysilicon layer;
- patterning the first photoresist layer with a first patterning process that reduces line edge roughness (LER);
- patterning a portion of the single polysilicon layer using the first patterned photoresist layer to form a plurality of first polysilicon structures having a layout symmetry associated therewith;
- forming a second photoresist layer over the plurality of first polysilicon structures and over a remaining unpatterned portion of the single polysilicon layer;
- patterning the second photoresist layer with a second patterning process that is different than the first patterning process;
- and
- patterning a portion of the remaining unpatterned portion of the single polysilicon layer to form one or more second polysilicon structures having a layout that is asymmetric with respect to the plurality of first polysilicon structures.
A method of forming a plurality of transistors, comprising:
- defining a plurality of active areas in a semiconductor body using one or more isolation regions;
- forming a gate dielectric over the active areas;
- forming a polysilicon layer over the gate dielectric in the active areas, and over the isolation regions;
- forming a first patterned photoresist layer, with a first patterning process that reduces line edge roughness (LER), over the polysilicon layer;
- patterning the polysilicon layer using the first patterned photoresist layer as an etch mask resulting in a first plurality of polysilicon structures, and an unpatterned portion of the polysilicon layer;
- removing the first patterned photoresist layer after forming the first plurality of polysilicon structures;
- forming a second patterned photoresist layer over the first plurality of polysilicon structures and over the unpatterned portion of the polysilicon layer with a second patterning process that is different than the first patterning process;
- patterning a portion of the unpatterned portion of the polysilicon layer using the second patterned photoresist layer as an etch mask to form one or more second polysilicon structures;
- and
- removing the second patterned photoresist layer after forming the one or more second polysilicon structures.
Dependencies are inferred from the claim text.