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US 2010/0163956 A1Published application
Eeprom device and method of manufacturing the same
AssigneeDongbu HiTek Co., Ltd.
InventorHyung-Keun Lee
Life of this patent
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Abstract
An EEPROM device may have, at the region where the control gate is formed, a gate oxide layer having a relatively smaller thickness than the gate oxide layer of the tunneling region by removing the gate oxide layer, at a predetermined thickness, at the region where the control gate is formed. Thus, integration of an EEPROM device may be maximized as a result of minimizing the area of the control gate.
Claims20
A device, comprising:
- a field oxide layer that defines an active region and a field region of a semiconductor substrate;
- conductive wells that respectively correspond to a tunneling region, a read transistor, and a control gate, under the active region of an upper surface of the semiconductor substrate;
- a gate oxide layer that is formed to have a relatively smaller thickness at the control gate than at the tunneling region, on the upper surface of the semiconductor substrate divided by the field oxide layer;
- and
- a polysilicon layer that is formed over the field oxide layer and the gate oxide layer from the tunneling region to the control gate.
2 more elements
A method comprising:
- forming conductive wells respectively corresponding to a tunneling region, a read transistor, and a control gate between field oxide layers formed on a semiconductor substrate;
- forming a gate oxide layer over the conductive wells;
- removing the gate oxide layer at a predetermined thickness from the control gate;
- and
- forming a polysilicon layer over the field oxide layer and the gate oxide layer.
2 more elements
Dependencies are inferred from the claim text.