Semiconductor device and method of manufacturing the same
OwnerTae Woong Jeonginventor
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Abstract
Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first polysilicon pattern formed on a semiconductor substrate, a second polysilicon pattern formed at a lateral side of the first polysilicon pattern such that the second polysilicon pattern extends to a height higher than the first polysilicon pattern, a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern, and a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern.
Claims10
A semiconductor device comprising:
- a first polysilicon pattern formed on a semiconductor substrate;
- a second polysilicon pattern formed at a lateral side of the first polysilicon pattern, wherein the second polysilicon pattern has a height higher than that of the first polysilicon pattern;
- a third polysilicon pattern formed in a region restricted by a top surface of the first polysilicon pattern and a lateral side of the second polysilicon pattern;
- and
- a contact electrically connecting the second polysilicon pattern and the third polysilicon pattern.
A method of manufacturing a semiconductor device, the method comprising:
- forming a stack of a first oxide layer pattern, a first polysilicon pattern, a second oxide layer pattern, and a first nitride layer pattern on a semiconductor substrate;
- forming a second polysilicon pattern having a form of a spacer while making contact with lateral sides of the first oxide layer pattern, first polysilicon pattern, second oxide layer pattern, and first nitride layer pattern stack on the semiconductor substrate;
- removing the first nitride layer pattern from between the second polysilicon pattern contacting the lateral sides of the first nitride layer pattern to form a control gate area;
- forming a pair of hard mask patterns having the form of a spacer in the control gate area, wherein the pair of hard mask patterns is formed on a top surface of the first polysilicon pattern and respective inner sidewalls of the second polysilicon pattern;
- forming first polysilicon floating gate patterns adjacent to each other by etching the first polysilicon pattern using the hard mask patterns as an etch mask until the semiconductor substrate is exposed at a central portion of the first polysilicon pattern;
- gap-filling a space between the first polysilicon floating gate patterns;
- forming a third polysilicon pattern in a region restricted by a top surface of the first polysilicon floating gate patterns and a lateral side of the second polysilicon pattern;
- and
- forming a contact electrically connected with the second polysilicon pattern and the third polysilicon pattern.
Dependencies are inferred from the claim text.