Recessed Access Device For A Memory

A memory device, comprising:

• at least one peripheral circuit positioned on a semiconductor substrate;
• and
• a memory array formed on the substrate that is operably coupled to the at least one peripheral circuit, the memory array including a recessed access device, the recessed device further comprising:
• a device recess formed in the substrate that extends to a first depth and including a gate oxide layer formed in the recess;
• an extended portion of the device recess that extends to a second depth that is greater that the first depth;
• a field oxide layer positioned within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate;
• active regions formed in the substrate that abut the field oxide layer;
• and
• a gate structure positioned in the device recess.

A memory array for a memory device, comprising:

• a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, wherein at least some of the plurality of memory cells comprise:
• a storage device;
• and
• a recessed access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the recessed access device further comprising:
• a device recess formed in the substrate that extends to a first depth and including a gate oxide layer formed in the recess;
• an extended portion of the device recess that extends to a second depth that is greater that the first depth;
• a field oxide layer positioned within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate;
• active regions formed in the substrate that abut the field oxide layer;
• and
• a gate structure positioned in the device recess.

A processing system at least partially formed on a semiconductor chip, comprising:

• a central processing unit (CPU);
• and
• a memory device operably coupled to the CPU by a communications bus, the memory device including at least one recessed access device further comprising:
• a device recess formed in the substrate that extends to a first depth and including a gate oxide layer formed in the recess;
• an extended portion of the device recess that extends to a second depth that is greater that the first depth;
• a field oxide layer positioned within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate;
• active regions formed in the substrate that abut the field oxide layer;
• and
• a gate structure positioned in the device recess.