Test ic structure

A test IC structure, disposed in a scribe line region of a wafer and comprising:

• a first test key, comprising a first active device and a first interconnect structure electrically connected to the first active device;
• a second test key, arranged substantially parallel with the first test key and comprising a second active device and a second interconnect structure electrically connected to the second active device;
• a first conductive plug, disposed over the first interconnect structure and contacting with an upmost metal layer of the first interconnect structure;
• a second conductive plug, disposed over the second interconnect structure and contacting with an upmost metal layer of the second interconnect structure;
• a first test pad, disposed over the first and the second test keys and contacting with the first conductive plug;
• a second test pad, disposed over the first and the second test keys and contacting with the second conductive plug;
• and
• a passivation layer over the scribe line region, having therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad.