Method and structure for integrating mim capacitors within dual damascene processing techniques

A metal-insulator-metal (MIM) capacitor structure, comprising:

• a lower interlevel dielectric (ILD) layer having a lower capacitor electrode formed therein;
• a selective metal cap formed on said lower capacitor electrode;
• a MIM capacitor dielectric structure formed over said selective metal cap;
• an upper ILD layer formed over said selective metal cap and said MIM capacitor dielectric structure;
• and
• an upper capacitor electrode structure formed in said upper ILD layer and in contact with said MIM capacitor dielectric structure.

A metal-insulator-metal (MIM) capacitor structure, comprising:

• a lower interlevel dielectric (ILD) layer having a lower capacitor electrode formed therein;
• a first dielectric capping layer formed on said lower ILD layer and said lower capacitor electrode;
• an upper ILD layer formed over said first dielectric capping layer;
• and
• an upper capacitor electrode structure formed in said upper ILD, said upper capacitor electrode structure further comprising:
• a plurality of via structures filled with an electrically conductive material, a bottom end of the via structures in contact with said first dielectric capping layer;
• and a conductive line structure in contact with a top end of the via structures.