Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers

A method for fabricating a semiconductor device, comprising:

• forming a first plate of a metal-insulator-metal (MIM) capacitor structure on a base structure, the base structure including contacts formed within a base layer;
• forming a first sacrificial layer on the first plate;
• forming a first etch tuning layer on the base structure adjacent to the first plate and the first sacrificial layer;
• removing the first sacrificial layer, and forming a first dielectric layer on the first etch tuning layer and the first plate;
• forming a second plate of the MIM capacitor structure on the first dielectric layer, and a second sacrificial layer on the second plate;
• forming a second etch tuning layer on the second sacrificial layer and the first dielectric layer, and planarizing such that the second etch tuning layer has a surface co-linear with surfaces of the second plate and the second sacrificial layer;
• removing the second sacrificial layer, and forming a second dielectric layer on the second etch tuning layer and the second plate;
• and
• forming a third plate of the MIM capacitor structure and a third etch tuning layer adjacent to the third plate on the third dielectric layer, wherein the etch tuning layers include materials for balancing etch depth during formation of a plurality of vias.