H03M 13/154
Error and erasure correction
Official title: {Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial}
H03M13/154 (Error and erasure correction) appears on 453 US grants and 424 published applications in this corpus.
Search patents in H03M- Granted patents
- 453
- Published applications
- 424
- Assignees
- 158
- Inventors
- 720
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 3 | 0 |
| 2000 | 2 | 0 |
| 2001 | 3 | 0 |
| 2002 | 4 | 2 |
| 2003 | 2 | 5 |
| 2004 | 1 | 2 |
| 2005 | 1 | 4 |
| 2006 | 4 | 7 |
| 2007 | 2 | 6 |
| 2008 | 4 | 6 |
| 2009 | 4 | 10 |
| 2010 | 6 | 11 |
| 2011 | 6 | 2 |
| 2012 | 17 | 4 |
| 2013 | 9 | 7 |
| 2014 | 10 | 7 |
| 2015 | 16 | 22 |
| 2016 | 18 | 32 |
| 2017 | 23 | 59 |
| 2018 | 39 | 42 |
| 2019 | 50 | 48 |
| 2020 | 60 | 51 |
| 2021 | 54 | 37 |
| 2022 | 53 | 22 |
| 2023 | 24 | 16 |
| 2024 | 17 | 12 |
| 2025 | 14 | 9 |
| 2026 | 3 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Storage system accommodating differing types of storage1 Sep 2026US 12,724,670 B2Everpure, Inc.
- Reliability coding with reduced network traffic2 Jun 2026US 12,645,538 B2Microsoft Technology Licensing, LLC
- Storage cluster utilizing differing load balancers10 Feb 2026US 12,549,632 B2Pure Storage, Inc.
- Method for supporting erasure code data protection with embedded PCIe switch inside FPGA+SSD23 Dec 2025US 12,505,053 B2Samsung Electronics Co., Ltd.
- Erasure code-based encoding method and related device2 Dec 2025US 12,489,467 B2Huawei Technoloiges Co., Ltd.
- Network-based erasure-coded memory reserve18 Jun 2026US 2026/0172472 A1International Business Machines Corporation
- Utilizing data processing units to optimize performance of an artifical intelligence storage system9 Oct 2025US 2025/0317491 A1Pure Storage, Inc.
- Digital signal symbol decision generation with confidence level based on error analysis25 Sep 2025US 2025/0300676 A1Mellanox Technologies, Ltd.
- Method and apparatus for computing syndromes, erasures and errors magnitudes in reed-solomon error correction28 Aug 2025US 2025/0274143 A1
- Transmission of pulse power and data over a wire pair3 Jul 2025US 2025/0216915 A1Cisco Technology, Inc.
Most cited
By later US patents
- Storage cluster407US 8,850,108 B1Pure Storage, Inc. · 2014
- Scheduling policy for queues in a non-volatile solid-state storage376US 8,874,836 B1Pure Storage, Inc. · 2014
- Architecture for soft decision decoding of linear block error correcting codes166US 6,381,726 B1Maxtor Corporation · 2002
- Method and apparatus for decoding code words protected wordwise by a non-binary BCH code from one or more symbol errors150US 5,297,153 AU. S. Philips Corporation · 1994
- Iterative concatenated convolutional Reed-Solomon decoding method149US 7,370,258 B2Sandbridge Technologies, Inc. · 2008