Low cost high performance EEPROM device
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsChandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Bai Yen Nguyen, Yoke Weng Tam
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Abstract
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
Claims20
A device comprising:
- a substrate prepared with a cell area separated by other active areas by isolation regions;
- and
- first and second transistors disposed in the cell area, wherein the first and second transistors comprise
- first and second lower sub-gates disposed over the substrate, and
- a common upper sub-gate disposed over the first and second lower sub-gates, wherein the common upper sub-gate is separated from the first and second lower sub-gates by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.
A device comprising:
- a substrate prepared with a cell area separated by other active areas by isolation regions;
- first and second lower sub-gates of first and second transistors in the cell area;
- a gate dielectric layer that separates the first lower sub-gate from a channel of the first transistor and the second lower sub-gate from a channel of the second transistor, wherein the gate dielectric layer comprises a tunneling window under the first lower sub-gate;
- a common upper sub-gate of the first and second transistors, wherein the common upper sub-gate and the first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates;
- and
- first and second intermediately doped buried regions in the substrate, wherein the buried doped regions extend beneath the first lower sub-gate.
Dependencies are inferred from the claim text.