Static random access memory and fabrication methods thereof

A method for fabricating a static random access memory, comprising:

• providing a semiconductor substrate;
• forming a plurality of transistors on the semiconductor substrate, the plurality of transistors comprising a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first transfer transistor, and a second transfer transistor;
• forming a single layer of a first interlayer dielectric layer covering the plurality of transistors;
• forming a plurality of openings only in the first interlayer dielectric layer to expose at least a gate of the first transfer transistor and a gate of the second transfer transistor;
• forming a first conductive via in each of the first openings in the first interlayer dielectric layer, the first conductive via being a single layer structure passing through the single layer of the first interlayer dielectric layer;
• forming a first metal layer over the first interlayer dielectric layer, the first metal layer comprising a word line electrically connecting the gate of the first transfer transistor and the gate of the second transfer transistor through the single layer structure of the first conductive via only passing through the single layer of the first interlayer dielectric layer;
• forming a second interlayer dielectric layer covering the first interlayer dielectric layer and the first metal layer;
• and
• forming a second metal layer over the second interlayer dielectric layer, the second metal layer comprising a first bit line, a second bit line, a first power source line and a second power source line electrically connecting with each of the plurality of the transistors via second conductive vias passing through the second interlayer dielectric layer.