Silicon designs for high voltage isolation
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsRicky Chow, Dominique Ho, Qian Tao
Life of this patent
Estimating the term…
Abstract
An isolation system, isolation capacitor, and Integrated Circuit are disclosed. The isolation capacitor is described to include a first capacitive element, a second capacitive element, a primary isolation layer positioned between the first and second capacitive elements, as well as a secondary isolation layer positioned between the first and second capacitive elements. The secondary isolation layer has an area that is larger than an area of one or both of the first and second capacitive elements, thereby reducing the likelihood of breakdown between the first and second capacitive elements.
Claims20
An isolation capacitor, comprising:
- a first capacitive element in electrical communication with a first circuit and having a first area;
- a second capacitive element in electrical communication with a second circuit that operates at a different voltage than the first circuit, wherein the second capacitive element comprises a second area;
- a primary isolation layer positioned between the first capacitive element and the second capacitive element, wherein the primary isolation layer substantially prohibits electrical current from flowing between the first capacitive element and second capacitive element;
- and
- a secondary isolation layer also positioned between the first capacitive element and the second capacitive element, wherein the secondary isolation layer comprises a third area that is larger than at least one of the first area and second area.
An isolation system, comprising:
- a first circuit operating at a first voltage range;
- a second circuit operating at a second voltage range that is different from the first voltage range;
- and
- an isolator that electrically isolates the first circuit from the second circuit while also enabling control signals to pass between the first circuit and second circuit in the form of electrical flux, wherein the isolator comprises:
- a first capacitive element in electrical communication with the first circuit;
- a second capacitive element positioned in an overlapping arrangement with the first capacitive element and in electrical communication with the second circuit;
- a primary isolation layer positioned between the first capacitive element and the second capacitive element;
- and
- a secondary isolation layer positioned between the first capacitive element and the second capacitive element, wherein the primary isolation layer and secondary isolation layer substantially prevent current from flowing directly between the first capacitive element and the second capacitive element, but enable the electrical flux to pass between the first capacitive element and the second capacitive element.
An Integrated Circuit, comprising:
- a substrate;
- a first dielectric material deposited on the substrate;
- a top metal plate positioned over the substrate and within the first dielectric material, wherein the top metal plate is in electrical communication with a first circuit;
- a bottom metal plate positioned over the substrate, beneath the top metal plate such that at least a portion of the bottom metal plate overlaps with at least a portion of the top metal plate thereby forming a capacitor therebetween, and within the first dielectric material, wherein the bottom metal plate is in electrical communication with a second circuit that operates at a different voltage than the first circuit;
- and
- a second dielectric material positioned between the top metal plate and the bottom metal plate, wherein the first dielectric material comprises SiO2, wherein the second dielectric material comprises a dielectric film containing SiN, wherein an area of the dielectric film is larger than the top metal plate and the bottom metal plate, wherein a passivation layer is provided over the top metal plate, and wherein at least a portion of the first dielectric material is also positioned between the bottom metal plate and the substrate.
Dependencies are inferred from the claim text.