Semiconductor device and method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Kook Park, Hongsoo Kim, Won-Chul Jang
Life of this patent
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Abstract
A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.
Claims19
A semiconductor device comprising:
- a substrate including an active region defined by a device isolation layer;
- a word line extending over the active region in a first direction;
- a plurality of interconnections extending over the word line in a second direction perpendicular to the first direction;
- a contact pad disposed between and spaced apart from the word line and the plurality of interconnections, the contact pad extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view;
- a lower contact plug electrically connecting the contact pad to the active region;
- and
- an upper contact plug electrically connecting the contact pad to one of the plurality of interconnections.
A semiconductor device comprising:
- a substrate including a cell array region and a peripheral circuit region;
- a cell array structure extending to a first height above the substrate over the cell array region;
- a peripheral logic structure extending to a second height smaller than the first height above the substrate over the peripheral circuit region;
- a plurality of parallel interconnections extending over the peripheral logic structure and the cell array structure;
- a contact pad disposed between a top surface of the peripheral logic structure and bottom surfaces of the plurality of interconnections, the contact pad overlapping with portions of the peripheral logic structure and portions of the plurality of interconnections when viewed from a plan view;
- a lower contact plug electrically connecting the peripheral logic structure to the contact pad;
- and
- an upper contact plug electrically connecting the contact pad to one of the plurality of interconnections,
- wherein the upper contact plug is laterally spaced apart from the lower contact plug in the first direction.
A semiconductor device comprising:
- a substrate having a top surface;
- a transistor structure formed on the substrate including source and drain regions on opposite sides of a transistor gate control signal line, the transistor gate control signal line extending in a first direction parallel to the top surface of the substrate;
- an insulating layer formed above the transistor structure;
- a first array of parallel contact pads formed above the insulating layer, each contact pad in the first array having a length in the first direction, a width in a second direction perpendicular to the first direction, and a height in a vertical direction perpendicular to the first and second directions, wherein the length is greater than the width and the height is greater than a vertical thickness of the transistor gate control signal line;
- and
- a lower contact plug electrically connecting one of the contact pads of the first array to the source region, the drain region or the transistor gate control signal line.
Dependencies are inferred from the claim text.