Semiconductor device

A semiconductor device, comprising:

• a gate trench across an active region of a semiconductor substrate;
• a gate structure filling the gate trench;
• and
• source/drain regions formed in the active region at respective sides of the gate structure, a buried channel region being defined in the active region between the source/drain regions,
• the gate structure including:
• a gate dielectric layer lining the gate trench;
• a barrier conductive pattern partially lining the gate dielectric layer, the barrier conductive pattern being located in at least a lower portion of the gate trench adjacent to a lower portion of the buried channel region;
• a gate conductive pattern in the gate trench, a topmost level of the gate conductive pattern being lower than an upper surface of the active region, an upper portion of the gate conductive pattern overlapping an upper portion of the buried channel region and a lower portion of the source/drain regions, and a lower portion of the gate conductive pattern overlapping the lower portion of the buried channel region;
• and
• an insulating capping layer stacked on the gate conductive pattern,
• wherein:
• the gate conductive pattern is formed of a metal material having a lower work function than the barrier conductive pattern,
• the barrier conductive pattern is between the gate conductive pattern and the gate dielectric layer in at least the lower portion of the gate trench adjacent to the lower portion of the buried channel region, and the upper portion of the gate conductive pattern directly contacts the gate dielectric layer.

A semiconductor device, comprising:

• a gate trench across an active region of a semiconductor substrate;
• a gate structure filling the gate trench;
• and
• source/drain regions formed in the active region at respective sides of the gate structure, a buried channel region being defined in the active region between the source/drain regions,
• the gate structure including:
• a gate dielectric layer lining the gate trench;
• a barrier conductive pattern partially lining the gate dielectric layer;
• a gate conductive pattern in the gate trench, a topmost level of the gate conductive pattern being lower than an upper surface of the active region, an upper portion of the gate conductive pattern overlapping an upper portion of the buried channel region and a lower portion of the source/drain regions, and a lower portion of the gate conductive pattern overlapping the lower portion of the buried channel region;
• and
• an insulating capping layer stacked on the gate conductive pattern,
• wherein:
• the gate conductive pattern is formed of a metal material having a lower work function than the barrier conductive pattern, and
• the barrier conductive pattern includes a first barrier conductive pattern between the lower portion of the gate conductive pattern and the gate dielectric layer, and a second barrier conductive pattern between the upper portion of the gate conductive pattern and the gate dielectric layer.