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US 9,041,054 B2Granted
High holding voltage electrostatic discharge protection device
AssigneeSofics BVBA
InventorsSven Van Wijmeersch, Olivier Marichal
Life of this patent
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Abstract
A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.
Claims30
An electrostatic discharge (ESD) protection circuit comprising:
- a first well, wherein the first well is lowly-doped and has an N-type conductivity;
- a second well, wherein the second well is lowly-doped and has a P-type conductivity;
- a first region formed within the first well, wherein the first region has the P-type conductivity and functions as an anode of the ESD protection circuit;
- a second region formed within the second well, wherein the second region has the N-type conductivity and functions as a cathode of the ESD protection circuit;
- a third region formed within the first well, wherein the third region is highly-doped and has the N-type conductivity;
- a fourth region formed within the second well, wherein the fourth region is highly-doped and has the P-type conductivity;
- a fifth region formed within the second well between the first well and the second region, wherein the fifth region is highly-doped and has the P-type conductivity;
- and
- a sixth region formed within the second well, wherein the sixth region is highly-doped, has the N-type conductivity, and is electrically coupled to the fifth region;
- wherein a first PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the second well;
- a first NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the first well;
- and
- a second NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the sixth region.
10 more elements
An electrostatic discharge (ESD) protection circuit comprising:
- a first well, wherein the first well is lowly-doped and has an N-type conductivity;
- a second well, wherein the second well is lowly-doped and has a P-type conductivity;
- a first region formed within the first well, wherein the first region has the P-type conductivity and functions as an anode of the ESD protection circuit;
- a second region formed within the second well, wherein the second region has the N-type conductivity and functions as a cathode of the ESD protection circuit;
- a third region formed within the first well, wherein the third region is highly-doped and has the N-type conductivity;
- a fourth region formed within the second well, wherein the fourth region is highly-doped and has the P-type conductivity;
- a fifth region formed within the first well between the first region and the second well, wherein the fifth region is highly-doped and has the N-type conductivity;
- and
- a sixth region formed within the first well, wherein the sixth region is highly-doped, has the P-type conductivity;
- and is electrically coupled to the fifth region;
- wherein a first PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the second well;
- a first NPN transistor is formed by an emitter including the second region, a base including the second well, and a collector including the first well;
- and
- a second PNP transistor is formed by an emitter including the first region, a base including the first well, and a collector including the sixth region.
11 more elements
Dependencies are inferred from the claim text.