Thin film transistor array panel and manufacturing method thereof

A thin film transistor array panel comprising:

• a substrate;
• a semiconductor layer formed on the substrate, the semiconductor layer including a source region and a drain region;
• at least one insulating layer formed on the semiconductor layer;
• a first contact hole and a second contact hole exposing at least portions of the source region and the drain region of the semiconductor layer and formed in the at least one insulating layer;
• a source electrode formed from a first layer of material, the source electrode substantially surrounding an outer perimeter of the first contact hole and formed on the at least one insulating layer;
• a drain electrode formed from the first layer of material, the drain electrode substantially surrounding an outer perimeter of the second contact hole and formed on the at least one insulating layer;
• a first connection electrode formed from a second layer of material different from the first layer, the first connection electrode connected to both the source region of the semiconductor layer and the source electrode through the first contact hole;
• and
• a second connection electrode formed from the second layer of material, the second connection electrode connected to both the drain region of the semiconductor layer and the drain electrode through the second contact hole.