Devices for monolithic data conversion interface protection and methods of forming the same

A method of manufacturing a protection device, the method comprising:

• forming a first semiconductor region of a first doping type in a substrate, wherein the first semiconductor region comprises a first well region;
• forming a second semiconductor region of a second doping type in the substrate, wherein the second semiconductor region comprises a second well region;
• forming a third semiconductor region of the first doping type in the substrate, wherein the third semiconductor region comprises a third well region, wherein the second semiconductor region is positioned between the first and third semiconductor regions;
• forming a fourth semiconductor region of the second doping type in the substrate, wherein the fourth semiconductor region comprises a fourth well region, wherein the third semiconductor region is positioned between the second and fourth semiconductor regions;
• forming a fifth well region of the first doping type in the substrate, wherein the fourth well region is positioned between the third and fifth well regions;
• forming a first diffusion region of the second type in the first semiconductor region;
• forming a first gate region adjacent the first semiconductor region;
• forming a second diffusion region of the first type in the second semiconductor region;
• forming a third diffusion region of the first type in the second semiconductor region;
• forming a fourth diffusion region of the second type in the third semiconductor region;
• forming a fifth diffusion region of the first type in the fourth semiconductor region;
• forming a second gate region adjacent the fourth semiconductor region;
• forming a signal node electrically connected to the first and fifth diffusion regions;
• forming a first power supply node electrically connected to the second and third diffusion regions;
• and
• forming a second power supply node electrically connected to the fourth diffusion region;
• wherein the second diffusion region, the second semiconductor region, the first semiconductor region and the first diffusion region are configured as a first silicon controlled rectifier (SCR);
• wherein the third diffusion region, the second semiconductor region, the third semiconductor region, and the fourth diffusion region are configured as a second SCR;
• wherein the fifth diffusion region, the fourth semiconductor region, the third semiconductor region and the fourth diffusion region are configured as a third SCR;
• wherein a junction between the first well region and the first diffusion region is configured as a first diode;
• wherein a junction between the fifth diffusion region and the fourth well region is configured as a second diode;
• and
• wherein a junction between the fifth well region and the fourth well region is configured as a third diode.