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US 8,946,821 B2Granted
SRAM integrated circuits and methods for their fabrication
AssigneeGlobalfoundries Inc.
InventorsMatthias Goldbach, Peter Baars
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Abstract
SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.
Claims11
An SRAM integrated circuit comprising:
- pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate;
- a layer of insulating material overlying the pull up and pull down transistors;
- pass gate transistors of the SRAM cell fabricated in and on a semiconducting layer overlying the layer of insulating material;
- a first metal-filled via extending through the layer of insulating material and coupled to a second metal layer;
- and
- a second metal-filled via extending through the layer of insulating material and coupled to a third metal layer;
- wherein the pull up and pull down transistors are interconnected as a pair of cross coupled inverters by the second metal layer and the third metal layer.
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A method for fabricating an SRAM integrated circuit comprising:
- fabricating pull up and pull down transistors of a six-transistor SRAM cell in and on a single silicon substrate;
- depositing a layer of insulator overlying the pull up and pull down transistors;
- forming pass gate transistors of the six-transistor SRAM cell in and on a semiconductor layer overlying the layer of insulator;
- and
- forming metal-filled vias extending through the layer of insulator and selectively coupling the pass gate transistors to the pull up and pull down transistors;
- wherein forming metal-filled vias extending through the layer of insulator comprises forming a first metal-filled via and a second metal-filled via extending through the layer of insulator, wherein the first metal-filled via is coupled to a second metal layer, the second metal-filled via is coupled to a third metal layer, and the pull up and pull down transistors are interconnected as a pair of cross coupled inverters by the second metal layer and third metal layer.
3 more elements
Dependencies are inferred from the claim text.