Methods for fabricating integrated circuits with improved patterning schemes

A method for fabricating an integrated circuit, the method comprising:

• patterning a non-ashable hard mask overlying an interlayer dielectric material and objects to be contacted;
• depositing an ashable planarization layer overlying the non-ashable hard mask;
• depositing an ashable pattern transfer layer overlying the ashable planarization layer;
• patterning a photoresist film overlying the ashable pattern transfer layer;
• etching the ashable pattern transfer layer using the photoresist film as a mask;
• etching the ashable planarization layer using the ashable pattern transfer layer as a mask to form trenches through the ashable planarization layer;
• and
• etching the interlayer dielectric material using the non-ashable hard mask and ashable planarization layer as a mask to form vias in the interlayer dielectric material.

A method for fabricating an integrated circuit, the method comprising:

• depositing an interlayer dielectric material overlying a semiconductor substrate;
• patterning a hard mask overlying the interlayer dielectric material;
• depositing a planarization layer overlying the hard mask;
• depositing a pattern transfer layer overlying the planarization layer;
• forming a photoresist overlying the pattern transfer layer;
• patterning the photoresist;
• determining whether the patterned photoresist is misaligned;
• and if the patterned photoresist is misaligned then performing a rework process comprising:
• removing the photoresist;
• re-forming the photoresist overlying the pattern transfer layer;
• and
• re-patterning the photoresist.