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US 8,786,989 B2Granted
Electronic device comprising a buffer and means for protecting against electrostatic discharges
AssigneeSTMicroelectronics S.r.l.
InventorsPhilippe Galy, Jean Jimenez
Life of this patent
Estimating the term…
Abstract
The electronic device comprises a first terminal and a second terminal, a buffer connected between the first terminal and the second terminal and comprising a signal input, and means for protecting against electrostatic discharges likely to occur across at least a pair of nodes of the buffer. The device comprises at least one integrated structure connected between the two nodes and said signal input, containing at least one MOS transistor and forming both said protection means and at least a part of said buffer.
Claims33
An integrated circuit comprising:
- a first terminal;
- a second terminal;
- a signal terminal;
- an integrated buffer and electrostatic discharge protection circuit connected between the first terminal and the second terminal, the integrated buffer and electrostatic discharge protection circuit comprising a MOS transistor configured to operate as part of both a buffer and an electrostatic discharge protection circuit;
- and
- logic circuitry configured to receive a logic signal from the buffer and to be protected against electrostatic discharge by the electrostatic discharge protection circuit.
3 more elements
An integrated circuit comprising:
- a first terminal;
- a second terminal;
- a signal terminal;
- and
- an integrated buffer and electrostatic discharge protection circuit connected between the first terminal and the second terminal, comprising at least one MOS transistor configured to operate at least transiently in a hybrid mode during an electrostatic discharge event occurring between the first or the second terminal and another terminal, wherein the at least one MOS transistor comprises a plurality of MOS transistors coupled in parallel with one another.
2 more elements
An integrated circuit comprising:
- a first terminal;
- a second terminal;
- a signal terminal;
- an integrated buffer and electrostatic discharge protection circuit connected between the first terminal and the second terminal, comprising at least one MOS transistor configured to operate at least transiently in a hybrid mode during an electrostatic discharge event occurring between the first or the second terminal and another terminal;
- and logic circuitry configured to receive a logic signal from the integrated buffer and to be protected against electrostatic discharge by the integrated electrostatic discharge protection circuit.
2 more elements
An integrated circuit comprising:
- a first terminal;
- a second terminal;
- a signal terminal;
- an integrated buffer and electrostatic discharge protection circuit connected between the first terminal and the second terminal, the integrated buffer and electrostatic discharge protection circuit comprising:
- a first MOS transistor having a current path coupled between the first terminal and the second terminal, wherein the first MOS transistor has a control terminal coupled to the signal terminal, and
- a control circuit coupled to a substrate contact of the first MOS transistor, the control circuit configured to control a substrate voltage of the MOS transistor;
- and
- a first additional MOS transistor of a conductivity type opposite from the first MOS transistor, the first additional MOS transistor having a current path coupled between the second terminal and a third terminal and having a control terminal coupled to the signal terminal.
5 more elements
An integrated circuit comprising:
- a first terminal;
- a second terminal;
- a third terminal;
- a first MOS transistor having a current path coupled between the first terminal and the second terminal, having a control terminal coupled to the third terminal, and having a substrate contact;
- a second MOS transistor having a current path coupled between the third terminal and the substrate contact of the first MOS transistor;
- a first resistive element coupled between the second terminal and the substrate contact of the first MOS transistor;
- a third MOS transistor coupled between the first terminal and the substrate contact of the first MOS transistor;
- and
- a second resistive element coupled between the third terminal and a substrate contact of the second MOS transistor.
6 more elements
A method of operating a semiconductor device that includes an integrated buffer and electrostatic discharge protection circuit comprising a MOS transistor, wherein the method comprises:
- during normal operation, buffering an input signal with the MOS transistor by:
- receiving the input signal at a gate of the MOS transistor;
- supplying a buffered output to an output terminal via a first source/drain terminal of the MOS transistor;
- during an electrostatic discharge event, operating the MOS transistor at least transiently in a hybrid mode to provide a discharge current path, wherein operating in the hybrid mode comprises:
- generating a MOS transistor type sub-threshold current in the MOS transistor;
- and
- generating a bipolar transistor type current in the MOS transistor dependent on a source-substrate voltage applied to the MOS transistor.
4 more elements
Dependencies are inferred from the claim text.