3D stacked array having cut-off gate line and fabrication method thereof

A three-dimensional stacked array having cut-off gate lines, comprising:

• a plurality of insulator strips formed in a word line direction and spaced apart with a regular interval so that each of the insulator strips has at least one neighboring insulator strip, each of the insulator strips having an insulating bottom line and projected insulating pillars formed of the same material in a bit line direction and at a regular interval on an etched semiconductor substrate;
• a plurality of semiconductor strips formed in the word line direction between the neighboring insulator strips, each of the semiconductor strips having a semiconductor bottom line and projected semiconductor pillars formed of the etched semiconductor substrate in the bit line direction with the same shape as each of the insulator strips;
• a plurality of cut-off gate lines formed in lower parts of trenches formed by the insulator strips and the semiconductor strips, a gate insulating layer being formed between each of the semiconductor strips and each of the cut-off gate lines;
• insulating layers having a tunneling oxide layer, a charge storage layer and a blocking oxide layer formed sequentially from and on each side wall of each of the trenches and each of the cut-off gate lines;
• and
• a plurality of word lines stacked on the insulating layers over each of the cut-off gate lines in each of the trenches, the word lines being interlaid with the same layers as the insulating layers,
• wherein
• the upper part of each of the projected semiconductor pillars is doped with impurities to have an impurity-doped layer and to form a bit line by each of the semiconductor strips,
• each of the semiconductor strips is formed of a single crystal semiconductor material having the same conductivity type except the upper parts doped with the impurities,
• the insulating bottom line is the region of each of the insulator strips that extends in the bit line direction under the cut-off gate lines, and
• the semiconductor bottom line is the region of each of the semiconductor strips that extends in the bit line direction under the cut-off gate lines.