Ferroelectric semiconductor transistor devices having gate modulated conductive layer

A semiconductor device, comprising:

• a semiconductor substrate;
• a first source/drain contact and a second source/drain contact formed on the semiconductor substrate;
• a control voltage contact;
• a gate structure formed on the semiconductor substrate, wherein the gate structure comprises:
• a conductive layer disposed over the semiconductor substrate;
• a ferroelectric layer disposed over the conductive layer;
• and
• a gate contact layer disposed over the ferroelectric layer;
• and
• wherein the conductive layer of the gate structure is electrically connected to the control voltage contact, and wherein the conductive layer is a non-semiconductor layer in direct contact with the control voltage contact.

A semiconductor device, comprising:

• a semiconductor substrate;
• a conductive layer formed directly on, and in contact with, the semiconductor substrate, the conductive layer formed of a non-semiconductor material having a thickness of three nanometers or less;
• and
• a ferroelectric layer disposed over the conductive layer, wherein the ferroelectric layer has an effective negative capacitance that counteracts a capacitance provided by the conductive layer;
• wherein the ferroelectric layer and the conductive layer form a gate structure of an FET device,
• a contact layer disposed over the ferroelectric layer;
• and
• a first source/drain contact and a second source/drain contact disposed on opposing sides of the gate structure, wherein the conductive layer is in direct contact with the first source/drain contact.

A semiconductor integrated circuit, comprising a semiconductor substrate, and a plurality of semiconductor devices formed on the semiconductor substrate, each of the plurality of semiconductor devices comprising:

• a first source/drain contact and a second source/drain contact formed on the semiconductor substrate;
• and
• a gate structure formed on the semiconductor substrate between the first and second source/drain contacts, wherein the gate structure comprises:
• a conductive layer disposed over the semiconductor substrate;
• a ferroelectric layer disposed over the conductive layer;
• and
• a gate contact layer disposed over the ferroelectric layer;
• wherein the conductive layer of the gate structure is electrically connected to the first source/drain contact, and wherein the conductive layer is a non-semiconductor layer in direct contact with the first source/drain contact.