Transient voltage suppressor without leakage current
AssigneeAmazing Microelectronic Corp.
InventorsChe-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
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AssigneeAmazing Microelectronic Corp.
InventorsChe-Hao Chuang, Kun-Hsien Lin, Ryan Hsin-Chin Jiang
Estimating the term…
A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
A transient voltage suppressor without leakage current, comprising:
A transient voltage suppressor without leakage current, comprising:
Dependencies are inferred from the claim text.