Low 1C screw dislocation 3 inch silicon carbide wafer
AssigneeCree, Inc.
InventorsAdrian Powell, Mark Brady, Stephan G. Mueller, Valeri F. Tsvetkov, Robert T. Leonard
Life of this patent
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Abstract
A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm−2 to about 2000 cm−2.
Claims21
A single crystal wafer of SiC having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 55 cm−2 to about 2500 cm−2.
A high quality semiconductor precursor wafer comprising:
- a single crystal silicon carbide wafer having a diameter of at least about 3 inches;
- said wafer having the 4H polytype;
- and
- said wafer having a 1 c screw density on its surface is from about 500 cm−2 to about 2500 cm−2.
A high quality semiconductor precursor wafer comprising:
- a single crystal silicon carbide wafer having a diameter of at least about 3 inches;
- said wafer having the 4H polytype;
- said wafer having a 1 c screw dislocation density on its surface is from about 500 cm−2 to about 2500 cm−2;
- and
- a Group III-nitride layer on said surface of said silicon carbide wafer.
A plurality of semiconductor device precursors comprising:
- a single crystal silicon carbide wafer having a diameter of at least about 3 inches and a 1 c screw dislocation density on the surface is from about 500 cm−2 to about 2500 cm−2;
- and
- a plurality of respective Group III-nitride epitaxial layers on some portions of said wafer.
A semiconductor wafer comprising:
- a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm−2 to about 2500 cm−2;
- and
- a plurality of devices on said silicon carbide substrate, each said device comprising:
- an epitaxial layer located on the substrate, said layer having a concentration of suitable dopant atoms for making the epitaxial layer a first conductivity type, and respective source, channel, and drain portions;
- a metal oxide layer on said channel portion;
- and
- and a metal gate contact on said metal oxide layer for forming an active channel when a bias is applied to said metal gate contact.
A semiconductor wafer comprising:
- a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm−2 to about 2500 cm−2;
- and
- a plurality of devices on said silicon carbide substrate, each said device comprising:
- a conductive channel on said substrate;
- a source and a drain on said conductive channel;
- and
- a metal gate contact between said source and said drain on said conductive channel for forming an active channel when a bias is applied to the metal gate contact.
A semiconductor wafer comprising:
- a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm−2 to about 2500 cm−2;
- and
- a plurality of junction field-effect transistors positioned on said single crystal silicon carbide substrate.
A semiconductor wafer comprising:
- a single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density is from about 500 cm−2 to about 2500 cm−2;
- and
- a plurality of hetero-field effect transistors positioned on said single crystal silicon carbide substrate.
A semiconductor wafer comprising:
- a bulk single crystal silicon carbide substrate of at least about 3 inches and having a 1 c screw dislocation density of less than 2500 cm−2, said bulk single crystal having respective first and second surfaces opposite one another;
- and
- a plurality of diodes positioned on said single crystal silicon carbide substrate.
A single crystal wafer of SiC having a diameter between about 3 inches and about 5 inches and a 1 c screw dislocation density from about 500 cm−2 to about 2500 cm−2.
Dependencies are inferred from the claim text.