Select transistor, method for making select transistor, memory device, and method for manufacturing memory device
AssigneeTokyo Electron Limited
InventorYoshitsugu Tanaka
Life of this patent
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Abstract
A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
Claims2
A method for manufacturing a memory device including a plurality of memory transistors connected in series and select transistors disposed in both ends of the plurality of memory transistors, comprising:
- forming a tunnel insulating layer on a semiconductor substrate;
- forming a charge storage layer on the tunnel insulating layer;
- forming a blocking insulating layer on the charge storage layer;
- selectively irradiating the blocking insulating layer in a region where the select transistor is to be formed, with a gas cluster ion beam containing argon as source gas;
- forming a gate electrode on the blocking insulating layer;
- patterning the tunnel insulating layer, the charge storage layer, blocking insulating layer and the gate electrode;
- and
- forming a source/drain region within the semiconductor substrate at both sides of the patterned gate electrode.
Dependencies are inferred from the claim text.