Integration of resistors and capacitors in charge trap memory device fabrication
AssigneeMicron Technology, Inc.
InventorsUmberto M. Meotto, Paolo Tessariol
Life of this patent
Estimating the term…
Abstract
A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.
Claims16
A method of fabricating a semiconductor device structure, the method comprising:
- forming a dielectric layer of a charge trapping dielectric stack for a non-volatile memory cell, the dielectric layer being disposed over a first conductor peripheral to the memory cell;
- patterning the dielectric layer to expose a portion of the first conductor;
- forming a conductive material over the dielectric layer and in contact with the exposed portion of the first conductor;
- and
- patterning the conductive material to form circuitry including the first conductor and to form a portion of the memory cell, the patterning of the conductive material further comprising removing a portion of the conductive material to form a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor.
The method of 1, wherein patterning the conductive material further comprises retaining a second portion of the conductive material contacting the first conductor to form conductive heads of a resistor.
A semiconductor device structure, comprising:
- a memory cell region of a substrate, the memory cell region including a non-volatile charge trapping dielectric stack;
- a peripheral region of the substrate, the peripheral region including a dielectric layer of the non-volatile charge trapping dielectric stack disposed over a first conductor;
- circuitry formed from a conductive material including the first conductor to form a portion of the semiconductor device structure as a resistor element;
- and
- a second conductor disposed over the first conductor, the second conductor being electrically isolated from a portion of the conductive material contacting the first conductor, the first conductor and the second conductor being dimensioned to form a capacitor.
A method of fabricating a semiconductor device structure, the method comprising:
- patterning a conductive layer into a transistor gate and at least one of a capacitor plate or a resistor in a peripheral region of the semiconductor device;
- depositing a dielectric layer as part of a non-volatile charge trapping dielectric stack of a memory cell in an array region of the semiconductor device;
- and
- patterning a portion of the dielectric layer disposed over the peripheral region to expose the entire transistor gate, but expose only a portion of the capacitor plate or expose only a portion of the resistor.
Dependencies are inferred from the claim text.