Inline method to monitor ONO stack quality

A method comprising:

• forming a structure including a charge-storage-layer overlying a tunneling-layer on a substrate;
• depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer;
• depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer;
• determining a differential voltage by calculating a difference between the first and second voltages;
• and
• determining from the differential tunneling voltage an operating characteristic of a non-volatile memory nonvolatile memory transistor comprising a charge-storage-layer and a tunneling-layer fabricated concurrently with the charge-storage-layer and tunneling-layer of the structure,
• wherein forming the structure comprises forming the structure on a monitor substrate processed concurrently with a product substrate on which the non-volatile memory transistor is fabricated.

A method comprising:

• forming a structure including a charge-storage-layer overlying a tunneling-layer on a substrate, wherein forming the structure comprises removing a blocking-dielectric-layer overlying the charge-storage-layer;
• depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure;
• depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure;
• determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltage;
• and
• determining from the differential tunneling voltage an operating characteristic of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer fabricated concurrently with the charge-storage-layer and tunneling-layer of the structure.

A method comprising:

• forming a structure including a charge-storage-layer overlying a tunneling-layer on a substrate;
• depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure;
• depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure;
• determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltage;
• and
• determining from the differential tunneling voltage an operating characteristic of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer fabricated concurrently with the charge-storage-layer and tunneling-layer of the structure,
• wherein forming the structure comprises forming the structure on a monitor substrate processed concurrently with a product substrate on which the non-volatile memory transistor is fabricated.