Nonvolatile memory device

A nonvolatile memory device comprising:

• a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars;
• a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars;
• a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillars, wherein the uppermost gate electrode layer includes a gate electrode layer for a selection transistor, and the gate electrode layers other than the uppermost gate electrode layer include gate electrode layers for memory cells;
• and
• first and second trenches isolating the plurality of gate electrode layers formed between the pair of first pillars and between the pair of second pillars, respectively,
• wherein the selection transistor of the first channel shares a gate electrode layer with the selection transistor of the second channel.