Method and apparatus for reducing implant topography reflection effect

An apparatus having a non-transitory computer-readable medium, the non-transitory computer-readable medium having instructions executable by a processor, the instructions comprising:

• instructions that determine a total light intensity exposure for a portion of a photoresist layer, wherein determining the total light intensity exposure for the portion of the photoresist layer includes determining a masked light intensity component and a reflected light intensity component;
• and
• instructions that create an optical proximity correction (OPC) model that uses the total light intensity exposure to identify a feature of an IC design layout that requires a local bias to compensate for a difference between a critical dimension (CD) of the feature of the IC design layout and the CD of a corresponding feature of the photoresist layer, wherein the OPC model identifies the difference by the reflected light intensity component exposure exceeding a predetermined threshold.

A method comprising:

• determining a total light intensity exposure for a portion of a photoresist layer, wherein determining the total light intensity exposure for the portion of the photoresist layer includes determining a masked light intensity component and a reflected light intensity component;
• and
• creating, by a computer, an optical proximity correction (OPC) model that determines whether the reflected light intensity component for the portion of the photoresist layer exceeds a predetermined value thereby causing a difference in a critical dimension (CD) of a feature of the IC design layout and a CD of a corresponding feature of the photoresist layer.

The method of 14, wherein determining the total light intensity exposure further comprises determining a product of the masked light intensity component and a reflection ratio, and

• wherein the reflection ratio is determined using a pattern density of a topography layer, a reflection index of the photoresist layer, and a reflection index of the topography layer.

The method of 14, further comprising:

• providing CD data related to a wafer produced using the IC design layout;
• and
• performing a regression analysis using the CD data to tune the OPC model.

The method of 19, wherein performing the regression analysis using the CD data to tune the OPC model comprises tuning the OPC model using after-development-inspection (ADI) data related to the wafer.