Circuit configurations to reduce snapback of a transient voltage suppressor

Abstract

This invention discloses a transient voltage suppressing (TVS) circuit that includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. The triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in an N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.

Dependencies are inferred from the claim text.