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US 8,541,893 B2Granted
Semiconductor memory device and power line arrangement method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Hoon Kim, Young-Chul Cho, Kwang-Il Park, Seong-Jin Jang
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Abstract
A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.
Claims35
A semiconductor memory device, comprising:
- a plurality of pads, each pad including an upper pad layer and a lower pad layer arranged below the upper pad layer, the plurality of pads including:
- (i) a first set of pads to be supplied with a first level of electrical power, and
- (ii) a second set of pads to be supplied with a second level of electrical power;
- a first pad power line arranged below the lower pad layers of the plurality of pads, the first pad power line extending in a direction crossing the plurality of pads so as to connect the first set of pads to each other;
- and
- a second pad power line arranged below the lower pad layers of the plurality of pads, the second pad power line extending in the direction crossing the plurality of pads so as to connect the second set of pads to each other.
3 more elements
Dependencies are inferred from the claim text.