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US 8,541,311 B2Granted
Integrated circuit fabrication methods utilizing embedded hardmask layers for high resolution patterning
AssigneeGlobalfoundries Inc.
InventorDmytro Chumakov
Life of this patent
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Abstract
Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.
Claims13
A method for fabricating an integrated circuit, comprising:
- depositing a dielectric layer over a semiconductor device;
- forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, wherein forming the plurality of trimmed hardmask structures comprises:
- depositing a trimmable hardmask layer over the dielectric layer including depositing polycrystalline silicon over the dielectric layer;
- patterning the trimmable hardmask layer to form a plurality of intermediate hardmask structures;
- and
- trimming the plurality of intermediate hardmask structures using a trimming process that selectively removes polycrystalline silicon over the dielectric layer to produce a plurality of trimmed hardmask structures over the dielectric layer;
- embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, wherein embedding the plurality of trimmed hardmask structures in the surrounding hardmask layer comprises depositing an organic planarizing layer over the plurality of trimmed hardmask structures;
- removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer;
- and
- etching the dielectric layer through the plurality of openings to form a plurality of etch features in the dielectric layer.
7 more elements
A method for fabricating an integrated circuit, comprising:
- depositing a dielectric layer over a plurality of electrical contact points of the integrated circuit;
- forming a composite hardmask layer over the dielectric layer, the composite hardmask layer comprising a surrounding hardmask layer in which a plurality of selectively-etchable features is embedded, each of the plurality of selectively-etchable features overlying a different one of the plurality of electrical contact points, and wherein forming the composite hard mask layer comprises:
- forming a trimmable hardmask layer over the dielectric layer including depositing polycrystalline silicon over the dielectric layer;
- lithographically patterning the trimmable hardmask layer including patterning the trimmable hardmask layer to form a plurality of intermediate hardmask structures;
- trimming the plurality of intermediate hardmask structures using a trimming process that selectively removes polycrystalline silicon over the dielectric layer to produce a plurality of trimmed hardmask structures over the dielectric layer, wherein the plurality of trimmed hard mask structures are the selectively-etchable features defined as a plurality of polycrystalline silicon blocks;
- and
- depositing the surrounding hardmask layer over the selectively-etchable features including depositing an organic planarizing layer over the plurality of polycrystalline silicon blocks such that the plurality of polycrystalline silicon blocks are embedded in the organic planarizing material;
- removing the plurality of selectively-etchable features to create a plurality of openings through the surrounding hardmask layer;
- and
- etching the dielectric layer through the plurality of openings to form a plurality of etch features in the dielectric layer.
7 more elements
A method for fabricating an integrated circuit, comprising:
- fabricating a plurality of semiconductor devices including a plurality of electrical contact points;
- depositing a dielectric layer over the plurality of electrical contact points;
- forming a trimmable hardmask layer over the dielectric layer including depositing polycrystalline silicon over the dielectric layer;
- lithographically patterning the trimmable hardmask layer to define a plurality of intermediate hardmask structures;
- trimming the plurality of intermediate hardmask structures using a trimming process that selectively removes polycrystalline silicon over the dielectric layer to produce a plurality of trimmed hardmask structures each overlying a different one of the electrical contact points;
- depositing an organic planarizing layer over the trimmed hardmask structures;
- planarizing the organic planarizing layer to expose the trimmed hardmask structures;
- removing the trimmed hardmask structures to form a plurality of openings in the organic planarizing layer;
- and
- etching the dielectric layer through the plurality of openings to form a plurality of etch features in the dielectric layer.
7 more elements
Dependencies are inferred from the claim text.