Optimization of critical dimensions and pitch of patterned features in and above a substrate

A semiconductor die comprising:

• a substrate device level comprising CMOS circuitry, the substrate device level having a substrate critical dimension comprising a smallest geometrical feature size which can be formed on the substrate device level;
• and
• a first above-substrate memory level formed above the substrate device level, the first above-substrate memory level comprising a plurality of memory cells and having a first above-substrate critical dimension comprising a smallest geometrical feature size which can be formed on the first above-substrate memory level, wherein the first above-substrate critical dimension is smaller than the substrate critical dimension,
• wherein the first above-substrate memory level comprises:
• a first area comprising portions of a first plurality of memory cells, the first plurality of memory cells having the first above-substrate critical dimension;
• a second area, said second area having a fan-out critical dimension, wherein said fan-out critical dimension is larger than the first above-substrate critical dimension, and wherein the first area further comprises a plurality of rails being interleaved.