Self-aligned metal oxide TFT with reduced number of masks

A method of fabricating metal oxide TFTs on transparent substrates using three masks and comprising the steps of:

• providing a transparent substrate having a front surface and a rear surface;
• patterning with a first mask opaque gate metal on the front surface of the substrate defining a gate area for a TFT;
• depositing a layer of transparent gate dielectric material on the front surface of the substrate overlying the gate metal and a surrounding area and a layer of transparent metal oxide semiconductor material on the surface of the layer of transparent gate dielectric;
• depositing a layer of etch stop material on the layer of metal oxide semiconductor material;
• patterning with a second mask positive photoresist material on the layer of etch stop material to define an isolation area in the layer of transparent metal oxide semiconductor material, the etch stop material and the photoresist material being selectively removable;
• removing uncovered portions of the layer of etch stop material, remaining portions of the layer of etch stop material forming a metal oxide semiconductor material etch mask;
• exposing the photoresist material from the rear surface of the substrate using the opaque gate metal on the front surface of the substrate as a mask and removing exposed portions of the photoresist material so as to leave the layer of etch stop material uncovered except for a portion overlying and aligned with the gate metal;
• using the metal oxide semiconductor material etch mask, etching uncovered portions of the metal oxide semiconductor material so as to isolate the TFT;
• using the portion of the photoresist material directly overlying and aligned with the gate metal, selectively etching uncovered portions of the etch stop layer leaving a portion of the etch stop layer overlying and aligned with the gate metal, the portion of the etch stop layer defining a channel area in the layer of metal oxide semiconductor material;
• and
• depositing and patterning with a third mask conductive material on the portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material to form source and drain areas on opposed sides of the channel area.