Semiconductor devices and methods of manufacture thereof

A capacitor, comprising:

• a first plate;
• a second plate;
• and
• an insulating material disposed between the first plate and the second plate, wherein the first plate and the second plate each comprise:
• a plurality of first parallel conductive members;
• a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members;
• a first base member coupled to an end of at least some of the plurality of first parallel conductive members;
• a second base member coupled to an end of at least some of the plurality of second parallel conductive members;
• and
• a connecting member disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member comprises at least one elongated via, wherein the at least one elongated via comprises a top portion and a bottom portion along a depth direction, wherein the at least one elongated via is wider at the top portion than in the bottom portion, wherein the top portion is adjacent the second base member relative to the bottom portion, and wherein the at least one elongated via is elongated along a length direction perpendicular to the depth direction wherein the connecting member comprises a third base member disposed between the first base member and the second base member.

A semiconductor device, comprising:

• a plurality of first parallel conductive members disposed over a workpiece, the plurality of first parallel conductive members having a first end and a second end;
• a connecting member disposed over and coupled at least to the plurality of first parallel conductive members, the connecting member comprising at least one elongated via, wherein along a depth direction the at least one elongated via comprises a top portion and a bottom portion, wherein the at least one elongated via is wider at the top portion than in the bottom portion, wherein the at least one elongated via is elongated along a length direction perpendicular to the depth direction;
• a plurality of second parallel conductive members disposed over and coupled to the connecting member, the plurality of second parallel conductive members having a first end and a second end;
• a first base member coupled to the first end of every other of the plurality of first parallel conductive members, the first base member electrically coupling an alternating plurality of first parallel conductive members together;
• and
• a second base member coupled to the second end of the plurality of first parallel conductive members not connected to the first base member, the second base member electrically coupling an alternating plurality of first parallel conductive members together, wherein the top portion is closer to the second base member than the bottom portion, wherein the connecting member further comprises a third base member disposed between the first base member and the second base member.

A method of manufacturing a capacitor, the method comprising:

• forming a first plate and a second plate over a workpiece;
• and
• forming a capacitor dielectric between the first plate and the second plate, wherein forming the first plate and the second plate each comprise:
• forming a plurality of first parallel conductive members;
• forming a plurality of second parallel conductive members over the plurality of first parallel conductive members;
• coupling a first base member to an end of at least some of the plurality of first parallel conductive members;
• coupling a second base member to an end of at least some of the plurality of second parallel conductive members;
• and
• forming a connecting member between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein forming the connecting member comprises forming at least one elongated via, wherein the at least one elongated via comprises a top portion and a bottom portion along a depth direction, wherein the at least one elongated via is wider at the top portion than in the bottom portion, wherein the top portion is adjacent the second base member relative to the bottom portion, and wherein the at least one elongated via is elongated along a length direction perpendicular to the depth direction, wherein the workpiece comprises a capacitor region and a conductive line region, and wherein the method comprises forming the plurality of first parallel conductive members, the connecting member, and the plurality of second parallel conductive members in the capacitor region;
• and
• forming a plurality of vias in the conductive line region when forming the at least one elongated via the plurality of vias comprising a minimum feature size.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first conductive material layer over a workpiece, the workpiece comprising a capacitor region and a conductive line region, the first conductive material layer including a first insulating material and a plurality of first parallel conductive members disposed within the first insulating material;
• forming a via layer over the first conductive material layer, the via layer including a second insulating material and a connecting member coupled to the first parallel conductive members, the connecting members being disposed within the second insulating material and comprising at least one elongated via;
• forming a second conductive material layer over the via layer, the second conductive material layer including a third insulating material and a plurality of second parallel conductive members disposed within the third insulating material, the plurality of second parallel conductive members being coupled to a connecting member, wherein the plurality of first parallel conductive members, the plurality of second parallel conductive members, and the connecting members comprise at least one capacitor plate, wherein the plurality of first parallel conductive members, the connecting members, and the plurality of second parallel conductive members are formed in the capacitor region;
• and
• forming a plurality of vias in the conductive line region when forming the via layer, the plurality of vias comprising a minimum feature size of the semiconductor device.