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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, Ying-Ju Chen, Yu-Wen Liu, Hao-Yi Tsai, Shin-Puu Jeng
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A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
A test pad interconnect structure for testing a plurality of integrated circuit dies formed in a semiconductor wafer, the interconnect structure comprising:
A test pad interconnect structure package for testing a plurality of integrated circuit dies formed in a semiconductor wafer, the interconnect structure package comprising:
A semiconductor wafer comprising:
Dependencies are inferred from the claim text.