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US 7,923,775 B2Granted
Semiconductor device and method for fabricating the same
AssigneeHynix Semiconductor Inc.
InventorsKwang-Ok Kim, Hye-Ran Kang
Life of this patent
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Abstract
A semiconductor device includes a plurality of trench patterns formed over a substrate; gate insulation layers formed over sidewalls of the trench patterns; gate electrodes formed over the trench patterns; line patterns coupling the gate electrodes; and source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trench patterns.
Claims7
A semiconductor device, comprising:
- a plurality of trench patterns formed over a substrate, the plurality of trench patterns defining a plurality of trenches;
- gate insulation layers formed over sidewalls of the trenches;
- gate electrodes formed in the trenches, wherein the gate electrodes completely fill inner spaces of the trenches on the gate insulation layer;
- line patterns coupling the gate electrodes;
- and
- source and drain regions formed in upper and lower portions of the substrate adjacent to the sidewalls of the trenches,
- wherein when the source region is formed in the upper portion of the substrate, the drain region is formed in the lower portion of the substrate, and when the source region is formed in the lower portion of the substrate, the drain region is formed in the upper portion of the substrate,
- wherein the source and the drain regions formed in the lower portions of the substrate are buried bit lines, the buried bit lines being not faced with a bottom surface of the gate electrodes and being faced with sidewalls of the gate electrodes.
5 more elements
A method for fabricating a semiconductor device, comprising:
- forming a plurality of trench patterns over a substrate, the plurality of trench patterns defining a plurality of trenches;
- forming gate insulation layers over sidewalls of the trenches;
- forming gate electrodes in the trenches, wherein the gate electrodes completely fill inner spaces of the trenches on the gate insulation layer;
- forming source and drain regions in upper and lower portions of the substrate adjacent to the sidewalls of the trenches;
- and
- forming line patterns coupling the gate electrodes,
- wherein when the source region is formed in the upper portion of the substrate, the drain region is formed in the lower portion of the substrate, and when the source region is formed in the lower portion of the substrate, the drain region is formed in the upper portion of the substrate,
- wherein the source and drain regions formed in the lower portions of the substrate are buried bit lines, the buried bit lines being not faced with a bottom surface of the gate electrodes and being faced with sidewalls of the gate electrodes.
5 more elements
Dependencies are inferred from the claim text.