Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer

A semiconductor device comprising:

• a first bit line and a second bit line which form a signal pair and to which a plurality of memory cells are connected;
• a sense amplifier formed from a presense amplifier and a CMOS flip flop;
• a first MOS transistor of the presense amplifier connected to the first bit line;
• a second MOS transistor of the presense amplifier connected to the second bit line;
• a third MOS transistor of the presense amplifier which is serially connected to the first MOS transistor, wherein the gate electrode of the third MOS transistor is connected to the second bit line;
• a fourth MOS transistor of the presense amplifier which is serially connected to the second MOS transistor, wherein the gate electrode of the fourth MOS transistor is connected to the first bit line;
• a first connection device which functions as a connection node between the serially-connected first and third MOS transistors, and connects a source area of one of the first and third MOS transistors to a drain area of the other of the first and third MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes;
• and
• a second connection device which functions as a connection node between the serially-connected second and fourth MOS transistors, and connects a source area of one of the second and fourth MOS transistors to a drain area of the other of the second and fourth MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

A semiconductor device comprising:

• a plurality of signal lines which are arranged at a predetermined pitch;
• first and second MOS transistors which are connected to the signal lines, and the first and second MOS transistors also being serially connected to each other;
• a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes;
• and
• third and fourth MOS transistors arranged in a manner such that the third and fourth MOS transistors are respectively adjacent to the first and second MOS transistors, wherein:
• the first, second, third, and fourth MOS transistors each have a gate electrode in an individual active area;
• between the adjacently-arranged first and third MOS transistors, an area interposed by the gate electrodes of the first and third MOS transistors is a common area of both transistors;
• and
• between the adjacently-arranged second and fourth MOS transistors, an area interposed by the gate electrodes of the second and fourth MOS transistors is a common area of both transistors.

A semiconductor device comprising:

• a pair of signal lines configured to transmit a pair of complementary signals, and are a first signal line and a second signal line;
• a first transistor coupled between the first signal line and a first common node, the first transistor including a gate electrode coupled to one of a control node and the second signal line;
• and
• a second transistor coupled between the first common node and a predetermined signal line, the second transistor including a gate electrode coupled to an other of the control node and the second signal line, and the second transistor includes a channel region larger in width than that of the first transistor.