Nonvolatile semiconductor memory

A nonvolatile semiconductor memory comprising:

• a plurality of first memory cell transistors which are connected in series to one another with a first gate spacing between each memory cell transistor and the adjacent one and share a source/drain diffusion layer between every two adjacent memory cell transistors;
• a second memory cell transistor which shares a source/drain diffusion layer with an endmost memory cell transistor of the series-connected memory cell transistors and is adjacent to the endmost memory cell transistor with a second gate spacing therebetween;
• and
• a first select gate transistor which shares a source/drain diffusion layer with the second memory cell transistor and is adjacent to the second memory cell transistor with a third gate spacing therebetween,
• wherein the first gate spacing is larger than the second gate spacing but smaller than the third gate spacing, and the source/drain diffusion layer shared by the second memory cell transistor and the first select gate transistor contains a region which is higher in impurity concentration than the source/drain diffusion layer shared by the memory cell transistors.