Method of manufacturing semiconductor device with recess gate transistor
AssigneeElpida Memory, Inc.
InventorYasushi Yamazaki
Life of this patent
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Abstract
A method of manufacturing a semiconductor device includes forming a plurality of recesses in a semiconductor substrate, forming a gate insulating film in the plurality of recesses, and a plurality of gate electrodes on the gate insulating film in the plurality of recesses, forming an insulating layer on the semiconductor substrate and the plurality of gate electrodes, forming a plurality of contact holes in the insulating layer, the contact holes being formed between adjacent ones of the plurality of gate electrodes, implanting a first impurity into the semiconductor substrate through the plurality of contact holes to form each of source and drain regions in contact with the gate insulating film.
Claims19
A method of manufacturing a semiconductor device, comprising:
- forming recess in a semiconductor layer of a first conductivity type;
- forming a gate insulating film in said recess, and a gate electrode structure over said gate insulating film, the gate electrode structure filling the recess and protruding from a surface of the semiconductor layer;
- forming a sidewall insulating film on a side surface of the gate electrode structure;
- introducing an impurity indicative of a second conductivity conductivity type by using the sidewall insulating film as a part of a mask, to form an impurity region of the second conductivity type in the semiconductor layer;
- forming an inter-layer insulating film on the gate electrode structure and the sidewall insulating film;
- and
- forming a contact hole in the inter-layer insulating film to expose a part of the sidewall insulating film,
- wherein said implanting said impurity indicative of the second conductivity type is performed after said forming said contact hole, and
- wherein said implanting said impurity indicative of the second conductivity type comprises using the inter-layer insulating film as another part of the mask.
A method of manufacturing a semiconductor device, comprising;
- forming a plurality of recesses in a semiconductor substrate;
- forming a plurality of gate electrodes in the plurality of recesses;
- forming an insulating layer having a plurality contact holes on the semiconductor substrate;
- implanting a first impurity into the semiconductor substrate through said plurality of contact holes to form source and drain regions in the semiconductor substrate;
- and
- forming an inter-layer insulating film on the plurality of gate electrodes, said implanting said first impurity comprising using said inter-layer insulating film as a mask.
A method of manufacturing a semiconductor device, comprising:
- forming first and second recesses in a semiconductor substrate;
- forming first and second gate structures respectively in the first and second recesses with an intervention of a gate insulating film, each of the first and second gate structures including a portion protruding from the semiconductor substrate;
- forming a first sidewall insulating film on a side surface of the portion of the first gate structure and a second sidewall insulating film on a side surface of the portion of the second gate structure, the first and second sidewall insulating films thereby forming a gap therebetween;
- forming an interlayer insulating film over the semiconductor substrate, first and second gate structures and first and second sidewall insulating films with filling the gap between the first and second sidewall insulating films by the interlayer insulating film;
- selectively removing the interlayer insulating film to form a hole, the hole being thereby defined by a left portion of the interlayer insulating film and by at least one part of each of the first and second sidewall insulating films;
- and
- introducing impurities through the hole by using the left portion of interlayer insulating film as a pan of a mask and the at least one part of each of the first and second sidewall insulating films as another part of the mask, one of source and drain regions being formed in a portion of the semiconductor substrate between the first and second gate structures.
Dependencies are inferred from the claim text.