Method of fabricating an integrated circuit

A method of fabricating an integrated circuit including the steps of:

• providing a semiconductor substrate;
• processing the semiconductor substrate to form memory cells;
• providing a mirror layer on the semiconductor substrate, the mirror layer covering the memory cells;
• processing the semiconductor substrate to form logic devices adjoining to said memory cells covered by said mirror layer, said forming of the logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected at least partly by said mirror layer;
• partly removing the mirror layer;
• and
• processing of the semiconductor substrate to form a wiring of the memory cells and of the logic devices, said remaining parts of the mirror layer being parts of the wiring of the memory cells.

A method of fabricating an integrated circuit including the steps of:

• providing a semiconductor substrate;
• processing of the semiconductor substrate to form a dynamic memory cell array including a plurality of memory cells, each memory cell having a storage capacitor and an access transistor with two source/drain regions and a gate region;
• retention annealing of the semiconductor memory cells;
• providing a mirror layer on the semiconductor substrate, the mirror layer covering the memory cell array;
• processing the semiconductor substrate to form logic transistor devices adjoining to said memory cells covered by said mirror layer, said forming of the logic transistor devices including activating the dopants in dopant regions by means of laser annealing or flash annealing, said radiation being reflected at least partly by said mirror layer;
• at least partly removing the mirror layer;
• and
• processing the semiconductor substrate to form a wiring of the memory cells and of the logic transistor devices.

A method of fabricating an integrated circuit including the steps of:

• providing a semiconductor substrate;
• processing of the semiconductor substrate to form a dynamic memory cell array including a plurality of memory cells, each memory cell having a storage capacitor and an access transistor with two source/drain regions and a gate region;
• retention annealing of the semiconductor memory cells;
• providing a metal layer on the semiconductor substrate, the metal layer covering the memory cell array and electrically contacting one of the source/drain regions of the transistors;
• processing the semiconductor substrate to form logic transistor devices adjoining to said memory cells covered by said metal layer, said forming of the logic transistor devices including forming dopant regions, and activating the dopants in the dopant regions by means of laser annealing or flash annealing;
• partly removing the metal layer, said remaining parts of the metal layer are contacts to the one source/drain regions of the access transistors;
• and
• processing the semiconductor substrate to form a wiring of the memory cells and of the logic transistor devices, said contacts being part of the wiring of the memory cells.