Layout for capacitor pair with high capacitance matching

An integrated circuit device comprising:

• a capacitor array comprising unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates;
• at least one first unit capacitor in each row and in each column of the capacitor array, the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have;
• at least one second unit capacitor in each row and in each column of the capacitor array, the at least one second unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have;
• and
• at least one third unit capacitor in each row and in each column of the capacitor array, the at least one third unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one third unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one third unit capacitors as other rows and columns have.

An integrated circuit device comprising:

• a capacitor array comprising unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates;
• at least one first unit capacitor in each row and in each column of the capacitor array, the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have;
• at least one second unit capacitor in each row and in each column of the capacitor array, the at least one second unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one second unit capacitors as other rows and columns have;
• at least one third unit capacitor connected to the at least one first unit capacitor;
• and
• at least one fourth unit capacitor connected to the at least one second unit capacitor, wherein the at least one third unit capacitor and the at least one fourth unit capacitor form an additional array, and wherein the at least one first unit capacitor is parallel connected to the at least one third unit capacitor, and the at least one second unit capacitor is parallel connected to the at least one fourth unit capacitor.

An integrated circuit device comprising:

• a common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus;
• a plurality of second fingers, each being between and electrically insulated from two of the first fingers;
• a second conductive bus interconnecting the plurality of second fingers;
• a plurality of third fingers, each being between and electrically insulated from two of the first fingers;
• a third conductive bus interconnecting the plurality of third fingers, wherein the plurality of first fingers, the plurality of second fingers, and the plurality of third fingers are metal lines in a metallization layer;
• and
• wherein the plurality of second fingers and the plurality of third fingers form an array with rows and columns, wherein, in each row and in each column, a number of the second fingers is equal to a number of the second fingers in other rows and columns, and wherein, in each row and in each column, a number of the third fingers is equal to a number of the third fingers in other rows and columns.

A capacitor pair comprising:

• a common node comprising a first conductive bus and a plurality of first fingers connected to the first conductive bus;
• a number of M*(M+N) second fingers, each second finger being between and electrically insulated from two of the first fingers, wherein M and N are non-zero integers;
• a second conductive bus interconnecting the second fingers;
• a number of N*(M+N) third fingers, each being between and electrically insulated from two of the first fingers;
• a third conductive bus interconnecting the third fingers, wherein the first fingers, the second fingers, and the third fingers are metal lines in a metallization layer;
• and
• wherein the second fingers and the third fingers form an array with M+N rows and M+N columns, wherein, in each row and in each column, there are M second fingers and N third fingers.