Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors

A test structure for inducing discharges during semiconductor wafer processing comprising:

• a planar parallel plate electrode having a first electrode plate comprising thin metal lines forming a first arcing electrode plate electrically connected on one end to a first metal structure comprising a first metal plate antenna, and a second electrode plate comprising thin metal lines forming a second arcing electrode plate adjacent said first electrode plate and having a gap distance from said first electrode plate, said second electrode plate connected on one end to a second metal structure comprising a second metal plate antenna;
• a dielectric between said first electrode plate and said second electrode plate, wherein said gap distance and said dielectric are predetermined such that arcs of predetermined strength will breakdown during testing and cause a short across said parallel plate electrode, said short of sufficient strength to damage circuitry on said wafer, while arcs of less strength will not break down during testing;
• a first metal probe pad, planar with said parallel plate electrode, electrically connected to said first metal plate antenna;
• a second metal probe pad, planar with said parallel plate electrode and said first metal probe pad, electrically connected to said second metal plate antenna;
• whereby said first and second metal plate antennas have a larger area than both said first and second arcing electrode plates and said first and second metal probe pads to accumulate charge thereon before it can discharge through said first and second arcing electrode plates for causing an arc and establishing a conductive circuit between said probe pads after arcing occurs across said parallel plate electrode.