US 7,609,493 B1 · ESD protection circuit and method for lowering capacitance of the ESD protection circuit

Abstract

An electrostatic discharge (ESD) protection circuit and a method for reducing capacitance in the ESD protection circuit. A pair of gated diodes are connected in series, wherein the anode of one of the gated diodes is coupled to a lower voltage supply node and the cathode the other gated diode is connected to the upper voltage supply node. The commonly connected anode and cathode of the series connected gated diodes are connected to an input/output pad and to receiver and driver circuitry. The gates of the gated diodes are connected together. A gate biasing circuit is connected to the gates of the gated diodes. The gate biasing circuit applies a voltage to the gates of the gated diodes and depletes their channel regions of charge carriers, which lowers the capacitances of each gate diode.

Claims12

Dependent claims

An electrostatic discharge (ESD) protection circuit, comprising:

first and second voltage supply rails;
a first gated diode having an anode, a cathode, and a gate, the cathode coupled to the first voltage supply rail;
and
a biasing circuit directly connected to the gate, wherein the biasing circuit comprises:
a first insulated gate field effect transistor having a control electrode, a first current carrying electrode, and a second current carrying electrode, the first current carrying electrode coupled to the gating node and the second current carrying electrode coupled the first voltage supply rail;
and
a second insulated gate field effect transistor having a control electrode, a first current carrying electrode, and a second current carrying electrode, the first current carrying electrode coupled to the control electrode of the first insulated gate field effect transistor, the second current carrying electrode coupled to the second voltage supply rail, and the control electrode coupled to the first voltage supply rail.

4 more elements

A capacitance modulation circuit suitable for use with electrostatic discharge (ESD) protection circuitry, comprising:

a first gated diode having an anode, a cathode, and a gating electrode;
a second gated diode having an anode, a cathode, and a gating electrode, the cathode coupled to the anode of the first gated diode, and the gating electrode of the second gated diode coupled to the gating electrode of the first gated diode to form a capacitance control node;
a first insulated gate field effect transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode directly connected to the capacitance control node;
and
a second insulated gate field effect transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode coupled to the control electrode of the first insulated gate field effect transistor.

2 more elements

Dependencies are inferred from the claim text.

ESD protection circuit and method for lowering capacitance of the ESD protection circuit

Life of this patent

ESD protection circuit and method for lowering capacitance of the ESD protection circuit

Life of this patent

Abstract

Claims12